The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) requires metallic wiring that connects individual devices in a semiconductor chip, to one another. One method of creating this wiring network on such a small scale is the dual damascene (DD) process schematically shown in FIG. 1. In the standard DD process, an interlayer dielectric (ILD), shown as two layers 110, 120 is coated on the substrate 100, FIG. 1a. The via level dielectric 110 and the line level dielectric 120 are shown separately for clarity of the process flow description. In general, these two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer.
A hard mask layer 130 is optionally employed to facilitate etch selectivity and to serve as a polish stop in a subsequent fabrication step. The wiring interconnect network includes two types of features: line features that traverse a distance across the chip, and the via features which connect together lines in different levels. Historically, both layers are made from an inorganic glass such as silicon dioxide (SiO2) or a fluorinated silica film deposited, for instance, by plasma enhanced chemical vapor deposition (PECVD).
In the dual damascene process, the position of the lines 150 and the vias 170 are defined lithographically in photoresist layer, 140, depicted in FIGS. 1b and 1d, and transferred into the hard mask, 130 and ILD layers, 110 and 120, using reactive ion etching processes. The process sequence shown in FIG. 1 is called a Line-first approach because the trench 160 which will subsequently house the line feature is etched first, see FIG. 1c. 
After the trench formation, lithography is used to define a via pattern 170 in the photoresist layer 140 which is transferred into the dielectric material, 110, to generate a via opening 180. See FIG. 1d. 
The dual damascene trench and via structure 190 is shown in FIG. 1e after the photoresist has been stripped. This structure 190 is coated with a conducting liner or material or material stack 200 that serves as an adhesion layer between the conductor and the ILD. This recess is then filled with a conducting fill material 210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper although other methods such as chemical vapor deposition (CVD) and other materials such as Al, Ag or Au and alloys thereof can also be used. The fill, 210, and liner, 200 materials are then chemically-mechanically polished (CMP) to be coplanar with the surface of the hard mask, 130, and the structure at this stage is shown in FIG. 1f. A capping material 220 can be deposited over the metal or as a blanket film, as is depicted in FIG. 1g to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional ILD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material 220. This process sequence is repeated for each level of the interconnect on the device. Since two interconnect features are defined to form a conductor in-lay within an insulator by a single polish step, this process is designated a dual damascene process.
In order to improve performance, the semiconductor industry has shrunk the gate length and as a result the chip size. As a consequence the interconnect structure that forms the metallic circuitry has also shrunk. Traditionally, the via levels are one of the most challenging to print with a high process latitude. In order to improve the manufacturability of the lithography step, advanced masks that incorporate phase-shifting, resolution enhancing techniques and optical proximity correction have been employed. Nevertheless, continuing efforts are underway to develop further improved interconnect fabrication techniques.